008. Implementation of a phase-locked loop in the GHz range

The phase-locked loop (PLL) is the beating heart of every modern wireless communication system by providing the local oscillator function in transceivers. Although, the phase-locked loop is omnipresent in the current information age, the design and realisation of such a loop remain challenging tasks. Most contemporary PLL architectures consist of four different basic building blocks, all combined in a feedback configuration (see figure): the voltage-controlled oscillator (VCO), the phase detector (PFD + CP), the digital frequency divider (DIV) and the loop filter (LF).

The goal of this master thesis is to develop a phase-locked loop that can generate spectrally pure oscillating signals in the GHz range. During this thesis you will:

  • Study the basic functioning of the PLL and perform a high-level system design of the different components.
  • Design and construct a PCB for the PLL with off-the-shelf components.
  • Measure the performance and accuracy of the developed prototype.

Interested or curious to know more? Feel free to contact Dries Peumans

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2021
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