Recently Xilinx introduced its family of RFSoC FPGAs. These FPGAs integrate multi-giga-sample RF data converters and soft-decision forward error correction (SD-FEC) into a SoC architecture, complete with an ARM® Cortex™-A53 processing subsystem. In order to evaluate these devices, a complete modem (as light as possible but as wideband as possible) or an- other suitable RF testbench should be developed. The objective of the thesis is to develop such a modem or testbench and to use it to evaluate the RFSoC RF performance.
Antwerp Space NV