40. Ad-Hoc ADC and DACS Using Passives and FPGA Digital IOS

Part count and power consumption for flight projects is a strong constraint, also the recent progress of the inclusion of data converters inside commercial FPGAs is not available for rad-hard FPGAs. The objective of the thesis is to use available FPGA digital I/O pins and passive components to implement and characterize simple analog-to-digital and digital-to-analog converters. For instance, the CMOS outputs could be used to create PWM based DACs, the LVDS IOs comparators could be used in a successive approximation ADC. The thesis will evaluate different architectures and demonstrate performance through the use of evaluation boards and breadboarding.

2019

Promoters

Yves Rolain
Antwerp Space NV
Back to top