Development of a Hardware-In-The-Loop Simulation and Testing Framework

In order to test the datapath of an FPGA-based digital signal processing subsystem, a data stream of test vectors needs to be applied to the input of the datapath and the output data needs to be checked for correctness. The objective of the thesis is to create a framework that offers an abstract interface to a high level language like C++, MatLab or Python, allowing it to be used in RTL simulation or on-target, ideally both in real-time, or via intermediate storage. This way the same simulation system can be used throughout the development process, from initial system simulation to hardware. As an additional benefit, the resulting framework could also provide hardware-in-the loop acceleration of system simulations.

2019

Promoters

Yves Rolain
Antwerp Space NV
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